Memory devices such as monolithic static random access memory (SRAM) devices and dynamic random access memory (DRAM) devices are typically tested prior to shipment by automated test equipment (ATE) referred to as “memory testers.” Memory testers typically include algorithmic pattern generators (APGs) that execute a test pattern or sequence on the memory device as the device under test (DUT). The APG operates under software control from a host system either separate from or integral with the memory tester. APGs typically generate and cycle through row and column addresses of memory locations in the memory device, and write or read data to the selected memory cell(s), in a systematic manner that is controlled by the host software without replicating the entire memory test pattern in separate memory in the memory tester.
While content addressable memory (CAM) devices may be tested on memory devices, they are typically tested on “logic testers” because logic testers typically are better configured to test the additional circuit components (e.g., instruction decoders, encoders, compare operations, mask cells or global masks) and more complicated interfaces (e.g., instruction buses, cascade interfaces) of the CAM devices. Logic testers typically do not include an APG; rather, they are instructed to generate and receive signals on a cycle-per-cycle basis according to test sequence information that is stored in a vector memory. The vector memory is loaded under software control by the host system that is either separate from or integral with the logic tester. Because each location in the vector memory typically stores one clock cycle worth of test sequence information, the total number of tests or memory locations that can be tested in the CAM DUT is limited by the total vector memory size of the logic tester. Additionally, as memory densities increase for DUTs, the required vector memory size of the tester also increases resulting in more expensive testers and higher test costs for the CAM supplier.
One approach used by test designers to reduce the number of vectors in a test sequence, and thus reduce the size of the vector memory, is to write software loops of test vectors. Loops could be used effectively to repeat the execution of a set of test vectors in a test sequence so long as the test data provided to the CAM DUT is the same from cycle to cycle, and the data expected to be received from the CAM DUT is the same from cycle to cycle, This approach, however, cannot, without utilizing more vector memory, accommodate test sequences that need to provide different inputs, or expect different outputs, from the CAM DUT from cycle to cycle. That is, vector-based logic testers typically cannot utilize variables inside a test loop without replicating the individual test inputs or outputs in the vector memory from cycle to cycle. Without the utilization of variables to create an indexing mechanism to aid in the generation, comparison and verification of unique data generated in a loop for a CAM DUT, the effectiveness of the looping technique, by itself, is limited.